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<h1>PCMPGTB/PCMPGTW/PCMPGTD—Compare Packed Signed Integers for Greater Than</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>0F 64 /<em>r</em><sup>1</sup></p>
<p>PCMPGTB <em>mm, mm/m64</em></p></td>
<td>RM</td>
<td>V/V</td>
<td>MMX</td>
<td>Compare packed signed byte integers in <em>mm</em> and <em>mm/m64</em> for greater than.</td></tr>
<tr>
<td>
<p>66 0F 64 /<em>r</em></p>
<p>PCMPGTB <em>xmm1</em>, <em>xmm2/m128</em></p></td>
<td>RM</td>
<td>V/V</td>
<td>SSE2</td>
<td>Compare packed signed byte integers in <em>xmm1 </em>and <em>xmm2/m128</em> for greater than.</td></tr>
<tr>
<td>
<p>0F 65 /<em>r</em><sup>1</sup></p>
<p>PCMPGTW <em>mm, mm/m64</em></p></td>
<td>RM</td>
<td>V/V</td>
<td>MMX</td>
<td>Compare packed signed word integers in <em>mm</em> and <em>mm/m64</em> for greater than.</td></tr>
<tr>
<td>
<p>66 0F 65 /<em>r</em></p>
<p>PCMPGTW <em>xmm1</em>, <em>xmm2/m128</em></p></td>
<td>RM</td>
<td>V/V</td>
<td>SSE2</td>
<td>Compare packed signed word integers in <em>xmm1 </em>and <em>xmm2/m128</em> for greater than.</td></tr>
<tr>
<td>
<p>0F 66 /<em>r</em><sup>1</sup></p>
<p>PCMPGTD <em>mm, mm/m64</em></p></td>
<td>RM</td>
<td>V/V</td>
<td>MMX</td>
<td>Compare packed signed doubleword integers in <em>mm</em> and <em>mm/m64</em> for greater than.</td></tr>
<tr>
<td>
<p>66 0F 66 /<em>r</em></p>
<p>PCMPGTD <em>xmm1</em>, <em>xmm2/m128</em></p></td>
<td>RM</td>
<td>V/V</td>
<td>SSE2</td>
<td>Compare packed signed doubleword integers in <em>xmm1</em> and <em>xmm2/m128</em> for greater than.</td></tr>
<tr>
<td>
<p>VEX.NDS.128.66.0F.WIG 64 /r</p>
<p>VPCMPGTB <em>xmm1, xmm2, xmm3/m128</em></p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Compare packed signed byte integers in <em>xmm2 </em>and <em>xmm3/m128</em> for greater than.</td></tr>
<tr>
<td>
<p>VEX.NDS.128.66.0F.WIG 65 /r</p>
<p>VPCMPGTW <em>xmm1, xmm2, xmm3/m128</em></p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Compare packed signed word integers in <em>xmm2 </em>and <em>xmm3/m128</em> for greater than.</td></tr>
<tr>
<td>
<p>VEX.NDS.128.66.0F.WIG 66 /r</p>
<p>VPCMPGTD <em>xmm1, xmm2, xmm3/m128</em></p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Compare packed signed doubleword integers in <em>xmm2</em> and <em>xmm3/m128</em> for greater than.</td></tr>
<tr>
<td>
<p>VEX.NDS.256.66.0F.WIG 64 /r</p>
<p>VPCMPGTB <em>ymm1, ymm2, ymm3/m256</em></p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX2</td>
<td>Compare packed signed byte integers in <em>ymm2 </em>and <em>ymm3/m256</em> for greater than.</td></tr>
<tr>
<td>
<p>VEX.NDS.256.66.0F.WIG 65 /r</p>
<p>VPCMPGTW <em>ymm1, ymm2, ymm3/m256</em></p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX2</td>
<td>Compare packed signed word integers in <em>ymm2 </em>and <em>ymm3/m256</em> for greater than.</td></tr>
<tr>
<td>
<p>VEX.NDS.256.66.0F.WIG 66 /r</p>
<p>VPCMPGTD <em>ymm1, ymm2, ymm3/m256</em></p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX2</td>
<td>Compare packed signed doubleword integers in <em>ymm2</em> and <em>ymm3/m256</em> for greater than.</td></tr>
<tr>
<td>
<p>EVEX.NDS.128.66.0F.W0 66 /r</p>
<p>VPCMPGTD k1 {k2}, xmm2, xmm3/m128/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Compare Greater between int32 vector xmm2 and int32 vector xmm3/m128/m32bcst, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr>
<tr>
<td>
<p>EVEX.NDS.256.66.0F.W0 66 /r</p>
<p>VPCMPGTD k1 {k2}, ymm2, ymm3/m256/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Compare Greater between int32 vector ymm2 and int32 vector ymm3/m256/m32bcst, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr>
<tr>
<td>
<p>EVEX.NDS.512.66.0F.W0 66 /r</p>
<p>VPCMPGTD k1 {k2}, zmm2, zmm3/m512/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Compare Greater between int32 elements in zmm2 and zmm3/m512/m32bcst, and set destination k1 according to the comparison results under writemask. k2.</td></tr>
<tr>
<td>
<p>EVEX.NDS.128.66.0F.WIG 64 /r</p>
<p>VPCMPGTB k1 {k2}, xmm2, xmm3/m128</p></td>
<td>FVM</td>
<td>V/V</td>
<td>AVX512VL AVX512BW</td>
<td>Compare packed signed byte integers in xmm2 and xmm3/m128 for greater than, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr>
<tr>
<td>
<p>EVEX.NDS.256.66.0F.WIG 64 /r</p>
<p>VPCMPGTB k1 {k2}, ymm2, ymm3/m256</p></td>
<td>FVM</td>
<td>V/V</td>
<td>AVX512VL AVX512BW</td>
<td>Compare packed signed byte integers in ymm2 and ymm3/m256 for greater than, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr></table>
<table>
<tr>
<td>
<p>EVEX.NDS.512.66.0F.WIG 64 /r</p>
<p>VPCMPGTB k1 {k2}, zmm2, zmm3/m512</p></td>
<td>FVM</td>
<td>V/V</td>
<td>AVX512BW</td>
<td>Compare packed signed byte integers in zmm2 and zmm3/m512 for greater than, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr>
<tr>
<td>
<p>EVEX.NDS.128.66.0F.WIG 65 /r</p>
<p>VPCMPGTW k1 {k2}, xmm2, xmm3/m128</p></td>
<td>FVM</td>
<td>V/V</td>
<td>AVX512VL AVX512BW</td>
<td>Compare packed signed word integers in xmm2 and xmm3/m128 for greater than, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr>
<tr>
<td>
<p>EVEX.NDS.256.66.0F.WIG 65 /r</p>
<p>VPCMPGTW k1 {k2}, ymm2, ymm3/m256</p></td>
<td>FVM</td>
<td>V/V</td>
<td>AVX512VL AVX512BW</td>
<td>Compare packed signed word integers in ymm2 and ymm3/m256 for greater than, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr>
<tr>
<td>
<p>EVEX.NDS.512.66.0F.WIG 65 /r</p>
<p>VPCMPGTW k1 {k2}, zmm2, zmm3/m512</p></td>
<td>FVM</td>
<td>V/V</td>
<td>AVX512BW</td>
<td>Compare packed signed word integers in zmm2 and zmm3/m512 for greater than, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr></table>
<p>NOTES:</p>
<p>1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A</em> and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A</em>.</p>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>FV</td>
<td>ModRM:reg (w)</td>
<td>EVEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>FVM</td>
<td>ModRM:reg (w)</td>
<td>EVEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>Performs an SIMD signed compare for the greater value of the packed byte, word, or doubleword integers in the destination operand (first operand) and the source operand (second operand). If a data element in the destination operand is greater than the corresponding date element in the source operand, the corresponding data element in the destination operand is set to all 1s; otherwise, it is set to all 0s.</p>
<p>The PCMPGTB instruction compares the corresponding signed byte integers in the destination and source oper-ands; the PCMPGTW instruction compares the corresponding signed word integers in the destination and source operands; and the PCMPGTD instruction compares the corresponding signed doubleword integers in the destina-tion and source operands.</p>
<p>In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).</p>
<p>Legacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The destination operand can be an MMX technology register.</p>
<p>128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The first source operand and destination operand are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.</p>
<p>VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The first source operand and destination operand are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM register are zeroed.</p>
<p>VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register.</p>
<p>EVEX encoded VPCMPGTD: The first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand (first operand) is a mask register updated according to the writemask k2.</p>
<p>EVEX encoded VPCMPGTB/W: The first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand (first operand) is a mask register updated according to the writemask k2.</p>
<h2>Operation</h2>
<p><strong>PCMPGTB (with 64-bit operands)</strong></p>
<pre>    IF DEST[7:0] &gt; SRC[7:0]
         THEN DEST[7:0) ← FFH;
         ELSE DEST[7:0] ← 0; FI;
    (* Continue comparison of 2nd through 7th bytes in DEST and SRC *)
    IF DEST[63:56] &gt; SRC[63:56]
         THEN DEST[63:56] ← FFH;
         ELSE DEST[63:56] ← 0; FI;</pre>
<p><strong>COMPARE_BYTES_GREATER (SRC1, SRC2)</strong></p>
<pre>    IF SRC1[7:0] &gt; SRC2[7:0]
    THEN DEST[7:0] (cid:197)FFH;
    ELSE DEST[7:0] (cid:197)0; FI;
(* Continue comparison of 2nd through 15th bytes in SRC1 and SRC2 *)
    IF SRC1[127:120] &gt; SRC2[127:120]
    THEN DEST[127:120] (cid:197)FFH;
    ELSE DEST[127:120] (cid:197)0; FI;</pre>
<p><strong>COMPARE_WORDS_GREATER (SRC1, SRC2)</strong></p>
<pre>    IF SRC1[15:0] &gt; SRC2[15:0]
    THEN DEST[15:0] (cid:197)FFFFH;
    ELSE DEST[15:0] (cid:197)0; FI;
(* Continue comparison of 2nd through 7th 16-bit words in SRC1 and SRC2 *)
    IF SRC1[127:112] &gt; SRC2[127:112]
    THEN DEST[127:112] (cid:197)FFFFH;
    ELSE DEST[127:112] (cid:197)0; FI;</pre>
<p><strong>COMPARE_DWORDS_GREATER (SRC1, SRC2)</strong></p>
<pre>    IF SRC1[31:0] &gt; SRC2[31:0]
    THEN DEST[31:0] (cid:197)FFFFFFFFH;
    ELSE DEST[31:0] (cid:197)0; FI;
(* Continue comparison of 2nd through 3rd 32-bit dwords in SRC1 and SRC2 *)
    IF SRC1[127:96] &gt; SRC2[127:96]
    THEN DEST[127:96] (cid:197)FFFFFFFFH;
    ELSE DEST[127:96] (cid:197)0; FI;</pre>
<p><strong>PCMPGTB (with 128-bit operands)</strong></p>
<pre>DEST[127:0] (cid:197)COMPARE_BYTES_GREATER(DEST[127:0],SRC[127:0])
DEST[MAX_VL-1:128] (Unmodified)</pre>
<p><strong>VPCMPGTB (VEX.128 encoded version)</strong></p>
<pre>DEST[127:0] (cid:197)COMPARE_BYTES_GREATER(SRC1,SRC2)
DEST[VLMAX-1:128] (cid:197) 0</pre>
<p><strong>VPCMPGTB (VEX.256 encoded version)</strong></p>
<pre>DEST[127:0] (cid:197)COMPARE_BYTES_GREATER(SRC1[127:0],SRC2[127:0])
DEST[255:128] (cid:197)COMPARE_BYTES_GREATER(SRC1[255:128],SRC2[255:128])
DEST[VLMAX-1:256] (cid:197) 0</pre>
<p><strong>VPCMPGTB (EVEX encoded versions)</strong></p>
<pre>(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 8
    IF k2[j] OR *no writemask*
         THEN
              /* signed comparison */
              CMP (cid:197) SRC1[i+7:i] &gt; SRC2[i+7:i];
              IF CMP = TRUE
                    THEN DEST[j] (cid:197) 1;
                    ELSE DEST[j] (cid:197) 0; FI;
         ELSE
                    DEST[j] (cid:197) 0
                                                    ; zeroing-masking onlyFI;
    FI;
ENDFOR
DEST[MAX_KL-1:KL] (cid:197) 0</pre>
<p><strong>PCMPGTW (with 64-bit operands)</strong></p>
<pre>    IF DEST[15:0] &gt; SRC[15:0]
         THEN DEST[15:0] ← FFFFH;
         ELSE DEST[15:0] ← 0; FI;
    (* Continue comparison of 2nd and 3rd words in DEST and SRC *)
    IF DEST[63:48] &gt; SRC[63:48]
         THEN DEST[63:48] ← FFFFH;
         ELSE DEST[63:48] ← 0; FI;</pre>
<p><strong>PCMPGTW (with 128-bit operands)</strong></p>
<pre>DEST[127:0] (cid:197)COMPARE_WORDS_GREATER(DEST[127:0],SRC[127:0])
DEST[MAX_VL-1:128] (Unmodified)</pre>
<p><strong>VPCMPGTW (VEX.128 encoded version)</strong></p>
<pre>DEST[127:0] (cid:197)COMPARE_WORDS_GREATER(SRC1,SRC2)
DEST[VLMAX-1:128] (cid:197) 0</pre>
<p><strong>VPCMPGTW (VEX.256 encoded version)</strong></p>
<pre>DEST[127:0] (cid:197)COMPARE_WORDS_GREATER(SRC1[127:0],SRC2[127:0])
DEST[255:128] (cid:197)COMPARE_WORDS_GREATER(SRC1[255:128],SRC2[255:128])
DEST[VLMAX-1:256] (cid:197) 0</pre>
<p><strong>VPCMPGTW (EVEX encoded versions)</strong></p>
<pre>(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 16
    IF k2[j] OR *no writemask*
         THEN
              /* signed comparison */
              CMP (cid:197) SRC1[i+15:i] &gt; SRC2[i+15:i];
              IF CMP = TRUE
                    THEN DEST[j] (cid:197) 1;
                    ELSE DEST[j] (cid:197) 0; FI;
         ELSE
                    DEST[j] (cid:197) 0
                                                    ; zeroing-masking onlyFI;
    FI;
ENDFOR
DEST[MAX_KL-1:KL] (cid:197) 0</pre>
<p><strong>PCMPGTD (with 64-bit operands)</strong></p>
<pre>    IF DEST[31:0] &gt; SRC[31:0]
         THEN DEST[31:0] ← FFFFFFFFH;
         ELSE DEST[31:0] ← 0; FI;
    IF DEST[63:32] &gt; SRC[63:32]
         THEN DEST[63:32] ← FFFFFFFFH;
         ELSE DEST[63:32] ← 0; FI;</pre>
<p><strong>PCMPGTD (with 128-bit operands)</strong></p>
<pre>DEST[127:0] (cid:197)COMPARE_DWORDS_GREATER(DEST[127:0],SRC[127:0])
DEST[MAX_VL-1:128] (Unmodified)</pre>
<p><strong>VPCMPGTD (VEX.128 encoded version)</strong></p>
<pre>DEST[127:0] (cid:197)COMPARE_DWORDS_GREATER(SRC1,SRC2)
DEST[VLMAX-1:128] (cid:197) 0</pre>
<p><strong>VPCMPGTD (VEX.256 encoded version)</strong></p>
<pre>DEST[127:0] (cid:197)COMPARE_DWORDS_GREATER(SRC1[127:0],SRC2[127:0])
DEST[255:128] (cid:197)COMPARE_DWORDS_GREATER(SRC1[255:128],SRC2[255:128])
DEST[VLMAX-1:256] (cid:197) 0</pre>
<p><strong>VPCMPGTD (EVEX encoded versions)</strong></p>
<pre>(KL, VL) = (4, 128), (8, 256), (8, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 32
    IF k2[j] OR *no writemask*
         THEN
              /* signed comparison */
              IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN CMP (cid:197) SRC1[i+31:i] &gt; SRC2[31:0];
                    ELSE CMP (cid:197) SRC1[i+31:i] &gt; SRC2[i+31:i];
              FI;
              IF CMP = TRUE
                    THEN DEST[j] (cid:197) 1;
                    ELSE DEST[j] (cid:197) 0; FI;
         ELSE
                    DEST[j] (cid:197) 0
                                                    ; zeroing-masking only
    FI;
ENDFOR
DEST[MAX_KL-1:KL] (cid:197) 0</pre>
<h2>Intel C/C++ Compiler Intrinsic Equivalents</h2>
<p>VPCMPGTB __mmask64 _mm512_cmpgt_epi8_mask(__m512i a, __m512i b);</p>
<p>VPCMPGTB __mmask64 _mm512_mask_cmpgt_epi8_mask(__mmask64 k, __m512i a, __m512i b);</p>
<p>VPCMPGTB __mmask32 _mm256_cmpgt_epi8_mask(__m256i a, __m256i b);</p>
<p>VPCMPGTB __mmask32 _mm256_mask_cmpgt_epi8_mask(__mmask32 k, __m256i a, __m256i b);</p>
<p>VPCMPGTB __mmask16 _mm_cmpgt_epi8_mask(__m128i a, __m128i b);</p>
<p>VPCMPGTB __mmask16 _mm_mask_cmpgt_epi8_mask(__mmask16 k, __m128i a, __m128i b);</p>
<p>VPCMPGTD __mmask16 _mm512_cmpgt_epi32_mask(__m512i a, __m512i b);</p>
<p>VPCMPGTD __mmask16 _mm512_mask_cmpgt_epi32_mask(__mmask16 k, __m512i a, __m512i b);</p>
<p>VPCMPGTD __mmask8 _mm256_cmpgt_epi32_mask(__m256i a, __m256i b);</p>
<p>VPCMPGTD __mmask8 _mm256_mask_cmpgt_epi32_mask(__mmask8 k, __m256i a, __m256i b);</p>
<p>VPCMPGTD __mmask8 _mm_cmpgt_epi32_mask(__m128i a, __m128i b);</p>
<p>VPCMPGTD __mmask8 _mm_mask_cmpgt_epi32_mask(__mmask8 k, __m128i a, __m128i b);</p>
<p>VPCMPGTW __mmask32 _mm512_cmpgt_epi16_mask(__m512i a, __m512i b);</p>
<p>VPCMPGTW __mmask32 _mm512_mask_cmpgt_epi16_mask(__mmask32 k, __m512i a, __m512i b);</p>
<p>VPCMPGTW __mmask16 _mm256_cmpgt_epi16_mask(__m256i a, __m256i b);</p>
<p>VPCMPGTW __mmask16 _mm256_mask_cmpgt_epi16_mask(__mmask16 k, __m256i a, __m256i b);</p>
<p>VPCMPGTW __mmask8 _mm_cmpgt_epi16_mask(__m128i a, __m128i b);</p>
<p>VPCMPGTW __mmask8 _mm_mask_cmpgt_epi16_mask(__mmask8 k, __m128i a, __m128i b);</p>
<p>PCMPGTB:__m64 _mm_cmpgt_pi8 (__m64 m1, __m64 m2)</p>
<p>PCMPGTW:__m64 _mm_pcmpgt_pi16 (__m64 m1, __m64 m2)</p>
<p>PCMPGTD:__m64 _mm_pcmpgt_pi32 (__m64 m1, __m64 m2)</p>
<p>(V)PCMPGTB:__m128i _mm_cmpgt_epi8 ( __m128i a, __m128i b)</p>
<p>(V)PCMPGTW:__m128i _mm_cmpgt_epi16 ( __m128i a, __m128i b)</p>
<p>(V)DCMPGTD:__m128i _mm_cmpgt_epi32 ( __m128i a, __m128i b)</p>
<p>VPCMPGTB:</p>
<p>__m256i _mm256_cmpgt_epi8 ( __m256i a, __m256i b)</p>
<p>VPCMPGTW:</p>
<p>__m256i _mm256_cmpgt_epi16 ( __m256i a, __m256i b)</p>
<p>VPCMPGTD:</p>
<p>__m256i _mm256_cmpgt_epi32 ( __m256i a, __m256i b)</p>
<h2>Flags Affected</h2>
<p>None.</p>
<h2>Numeric Exceptions</h2>
<p>None.</p>
<h2>Other Exceptions</h2>
<p>Non-EVEX-encoded instruction, see Exceptions Type 4.</p>
<table class="exception-table">
<tr>
<td>EVEX-encoded VPCMPGTD, see Exceptions Type E4.</td></tr>
<tr>
<td>EVEX-encoded VPCMPGTB/W, see Exceptions Type E4.nb.</td></tr></table></body></html>